1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit technology. More particularly, the present invention relates to a CMOS integrated circuit for lessening latch-up susceptibility.
2. Description of the Related Art
Although CMOS-based integrated circuitry is characterized by low-power consumption and high-density integration, devices such as transistors or resistors parasitic onto semiconductor substrates raise a reliability issue to be considered. Referring to FIG. 1, a conventional CMOS circuit fabricated onto a semiconductor substrate is schematically illustrated in a cross-sectional view. In the drawing, reference numeral 10 denotes a P-type semiconductor substrate in which an N-well 11 is provided. A PMOS transistor 12 is formed on the N-well 11, whereas an NMOS transistor 13 is formed on the P-type semiconductor substrate 10. An N-type doped region 14 and a P-type doped region 15 are formed in the N-well 11 and the P-type semiconductor substrate 10 to form the contact regions, respectively.
In FIG. 1, a pair of spaced apart P-type doped regions 12S and 12D serve as the source and the drain of the PMOS transistor 12, while its gate 12G is disposed to cover a portion of the N-well 11 between the source 12S and the drain 12D. A pair of spaced apart N-type doped regions 13S and 13D serve as the source and the drain of the NMOS transistor 13, while its gate 13G is disposed to cover a portion of the P-type semiconductor substrate 10 between the source 13S and the drain 13D. The PMOS transistor 12 is configured with the gate 12G electrically connected to the gate 13G of the NMOS transistor 13 to form an input terminal V.sub.IN, while the drains 12D and 13D are tied together to form an output terminal V.sub.OUT. Both the source 12S of the PMOS transistor 12 and the N-type doped region 14 are powered by a voltage source V.sub.DD, and the source 13S of the NMOS transistor 13 and the P-type doped region 15 is powered by another voltage source V.sub.SS.
As shown in FIG. 1, the source 12S of the PMOS transistor 12, N-well 11, and P-type semiconductor substrate 10 constitute the emitter, base, and collector of a parasitic PNP bipolar junction transistor Q.sub.1, respectively. Moreover, the source 13S of the NMOS transistor 13, P-type semiconductor substrate 10, and N-well 11 constitute the emitter, base, and collector of a parasitic NPN bipolar junction transistor Q.sub.2, respectively. In the drawing, R.sub.W designates one parasitic resistor spread over the N-well 11, and R.sub.SUB designates another parasitic resistor spread over the P-type semiconductor substrate 10.
However, when a voltage level higher than V.sub.DD or lower than V.sub.SS occurs at the output terminal V.sub.OUT on account of interference or noise, the emitter-base junctions of the parasitic transistors Q.sub.1 and Q.sub.2 will enter forward bias to conduct a current flowing therethrough. Even worse, the path between V.sub.DD and V.sub.SS is short-circuited so as to cause permanent damage to the integrated circuit. This is the so-called latch-up effect.
U.S. Pat. No. 4,947,227 discloses a latch-up resistant CMOS structure achieved by patterning a semiconductor substrate into a trench, on the inside surface of which an oxide insulating layer is thermally grown. Thereafter, amorphous silicon or polysilicon is deposited on the surface of the semiconductor and substantially fills the trench to form a well region. However, grain boundaries contained in the amorphous silicon or polysilicon will deteriorate the carrier mobility of transistors fabricated within such a well region.
In addition, U.S. Pat. No. 5,338,986 discloses a latch-up resistant CMOS output circuit achieved by increasing the source-gate spacing to dispose a resistance device at the source of the PMOS transistor or NMOS transistor and thus reduce the collector current of the parasitic transistor. However, U.S. Pat. No. 5,338,986 merely takes minority carriers into account, but secondary triggering induced by majority carriers results in a low holding-voltage and possibly a short-circuit of V.sub.DD -V.sub.SS causing permanent damage to the integrated circuit.